As operating frequencies of integrated circuit (IC) chips increase, clock uncertainty, such as, for example, clock jitter, becomes an increasingly significant part of a timing budget for clocks associated with such chips. However, accurately quantifying clock jitter by simulation or off-chip measurement can be difficult.
Many high-frequency clocks, for example, are synthesized on-chip by a phase locked loop (PLL), the output of which can be divided down to lower frequencies. Each clock of the chip can be distributed to on-chip clock users such as flip-flops or latches via a clock tree that includes a network of wires and buffers. The mixed-signal, high-frequency nature of the PLL and the distributed sources of clock jitter in the clock tree such as cross-talk and power supply noise are difficult to model for simulation.
Bringing the clock off-chip for measurement can involve sending a generated clock signal through an output driver and printed circuit board traces or other similar components for observation by an oscilloscope or other instrument for measuring jitter. Off-chip techniques can further include dividing the clock frequency to lower frequencies to accommodate limitations of the output driver. Thus, an off-chip measurement path typically includes additional equipment and other sources of timing jitter that can introduce significant timing uncertainty to measured clock jitter, which can lead to inaccurate results.
A simulation or off-chip measurement that provides a jitter estimate that is greater than the actual jitter can lead to unnecessary limitation of the operating frequency of an IC chip, which can reduce performance speed of an chip. Jitter estimates that are lower than the actual jitter can lead to timing errors that result in poor reliability or yields of an IC chip and/or missed manufacturing schedules and budgets due to expensive and time-consuming revisions of mask sets used to fabricate the IC chip.